1. Field of the Invention
This invention relates to a method of manufacturing a thin film transistor (TFT) having a crystalline semiconductor channel formed from a silicon film having been crystallised using a crystallisation enhancing material (CEM), and to a TFT manufactured using the same. The invention further relates to an active matrix device, especially an active matrix liquid crystal display (AMLCD), comprising a row and column array of active elements wherein each element is associated with such a TFT by connection to corresponding row and column conductors.
2. Description of the Related Art
Conventionally, polysilicon (poly-Si) crystalline silicon films used in TFTs have been manufactured by depositing an amorphous silicon (a-Si) film on an insulating substrate and crystallising the a-Si film by exposing it to a high temperature for a prolonged period of time, typically in excess of 600xc2x0 C. for up to 24 hours.
As an alternative, U.S. Pat. No. 5,147,826 discloses a lower temperature method of crystallising an a-Si film. The method comprises the steps of depositing a thin film of a CEM such as Nickel on the a-Si film and annealing the films at a temperature below that which would be required to produce crystalline growth in the absence of the CEM. The CEM stimulates crystal growth at temperatures below 600xc2x0 C. and also provides more rapid crystal growth than would otherwise occur. For example, a typical anneal using the method of U.S. Pat. No. 5,147,826 might be at around 550xc2x0 C. for 10 hours. This represents an improvement over non-CEM methods for at least two reasons: first, it enables low cost non-alkali glass substrates such as borosilicate to be used which would normally suffer glass compaction and warpage at temperatures of 600xc2x0 C. or more; and secondly, as the anneal duration is reduced, the manufacturing throughput rate is increased and therefore the associated manufacturing cost may be reduced.
In a further development of this method, U.S. Pat. No. 5,543,352 discloses improving the resultant crystallinity by irradiating the film with a laser light. Without wishing to be bound by any theory, it is believed that the effect of this is to melt the grain boundaries between the highly orientated  less than 111 greater than  crystalline silicon grains and to reform them to produce atomically continuous grain boundaries. The resultant crystalline structure has been referred to in the art as continuous grain silicon. Both U.S. Pat. No. 5,147,826 and U.S. Pat. No. 5,543,352 are incorporated hereinafter by reference.
In so far as exposing a-Si to a CEM is concerned, it is known to do this by either applying the CEM to an a-Si film already deposited, or by first depositing the CEM and subsequently depositing the a-Si film thereover. Further known is the direct application of the CEM to the a-Si, for example by sputtering, or application of a CEM as a solute in solution, for example Nickel dissolved in an acetate solution as described in Example 1 of U.S. Pat. No. 5,543,352. In none of the above examples does the application of the CEM provide the TFT with structural support.
From U.S. Pat. No. 5,476,810, it is known to manufacture an electronic device comprising a thin film circuits using a metal foil as a temporary support.
It is an object of the present invention to provide a method of manufacturing a TFT in which application of a CEM used to promote crystallisation may be further used to enhance the structural integrity of the TFT.
Therefore, in accordance with a first aspect of the present invention, there is provided a method of manufacturing a thin film transistor (TFT) comprising source and drain electrodes joined by a semiconductor channel formed from a semiconductor layer, a gate insulating layer and a gate electrode, the method comprises the steps of:
over a supporting substrate, depositing the semiconductor layer and applying a foil comprising a crystallisation enhancing material (CEM); and
heating the semiconductor layer, ideally to a temperature not exceeding 600xc2x0 C., so as to crystallise the semiconductor layer from regions exposed to the CEM of the foil.
Using this method, the foil can be used to provide the TFT with additional structural integrity. In particular, if the foil is applied first on the supporting substrate and the semiconductor layer deposited thereafter, it may be then possible to remove the TFT structure including foil from the supporting substrate at the interface between the foil and the supporting substrate. The foil may then be optionally replaced with an alternative supporting layer, for example, a flexible plastic layer.
By applying a foil, what is meant is the application on to the supporting substrate of a thin flexible sheet of material which may for example be stored on a roll prior to its application. Also, a foil comprising a CEM would include a foil having CEM particles distributed throughout it, a foil having a continuous or discontinuous CEM coating or a foil consisting substantially entirely of the CEM, impurities aside.
The method may further comprise the step of providing a patterned barrier layer between the foil and the semiconductor layer wherein the semiconductor layer is crystallised from regions exposed through vias in the barrier layer to the CEM of the foil. In particular, the barrier layer may be formed as a metal oxide of the foil or alternatively be separately deposited, for example, a silicon oxide layer deposited by plasma CVD.
Use of a barrier layer may prevent over exposure of the a-Si film to a CEM which is desirable as such overexposure can reduce the quality of crystallinity and adversely affect the electrical characteristics of the resultant TFT. For example, when the CEM is a metal and therefore a conductor, such overexposure can cause undesirable current leakage in the resultant TFT.
From regions of the semiconductor layer exposed through vias in the barrier layer to the CEM of the foil, further crystalline growth may occur laterally though the semiconductor layer extending to regions otherwise protected from the CEM by the barrier layer. Such laterally crystallised regions typically contain higher quality crystallinity than the regions exposed to the CEM.
Furthermore, where such lateral crystallisation occurs, the semiconductor layer may be etched after crystallisation to form the semiconductor channel whereby etching removes the regions of the semiconductor layer exposed through vias in the barrier layer to the CEM of the foil, i.e. leaving only the high quality laterally crystallised regions.
Also provided in accordance with the first aspect of the present invention is a TFT comprising source and drain electrodes joined by a semiconductor channel, a gate insulating layer and a gate electrode, all mounted on a foil comprising a crystallisation enhancing material (CEM). According to a second aspect of the present invention, an active matrix device is provided comprising a row and column array of active elements wherein each element is associated with a switching TFT of the aforementioned type and connected to corresponding row and column conductors.
Also provided in accordance with the second aspect of the present invention is an active matrix device comprising a row and column array of active elements wherein each element comprises a switching TFT connected to corresponding row and column conductors, all mounted on a foil comprising a crystallisation enhancing material (CEM).
According to a third aspect of the present invention, a method of manufacturing an active matrix device is provided comprising a row and column array of active elements wherein each element is associated with a switching TFT comprising source and drain electrodes joined by a semiconductor channel, a gate insulating layer and a gate electrode, and connected to corresponding row and column conductors. The method comprising the steps of exposing a semiconductor layer to a crystallisation enhancing material so as to crystallise the semiconductor layer from regions exposed to the CEM, and forming the semiconductor channel therefrom; and providing plastic, ideally flexible, supporting substrates either side of the active element array.